Integrated circuits are typically provided with electrostatic discharge (ESD) protection circuitry between the external pins of the device and the main circuit in order to shunt ESD pulses safely to ground and thereby prevent damage to the integrated circuit. Typical ESD pulses can easily exceed 2000 Volts and deliver peak currents of 1 to 30 Amperes within a rapid rise time of 1 to 10 nanoseconds followed by a slow decay in electrical current over the next 100 nanoseconds or so. As a normal part of quality control following integrated circuit manufacture, the ESD protection circuitry is tested. An ESD test normally involves applying a standard electrical waveform representative of one or more ESD events to the various external pins of the manufactured device and observing whether or not the ESD protection circuitry associated with each of those pins adequately handles the test waveform within specified tolerances.
Unfortunately, it has been observed that, notwithstanding the presence of ESD protection circuitry manufactured to design specifications, the very act of ESD testing can, under certain circumstances, create damaging hot spots (stored charge) within an integrated circuit. This is particularly the case when the power supply pin is being tested. The power supply pin is connected to many circuit elements in the main circuit in order to provide the electric power needed for its normal operation. Integrated circuits may also include large capacitive nodes (long conductive lines), which can be coupled through such circuit elements to the power supply pin.
For example, FIG. 1 shows a typical CMOS inverter comprising p-channel and n-channel transistors P1 and N1. The p-channel transistor P1 of this inverter is connected to the power supply (VCC) pin. A conductive line 5 forms a high capacitance node B at the output of this inverter. Accordingly, in this circuit the high capacitive node B is coupled to the VCC pin by the transistor P1. For an ESD test of the VCC pin, the chip is placed in a standby mode. However, this may not guarantee that the transistor P1 will remain of during an ESD test. If node A on the input side of the inverter happens to be at a logic 0 voltage level when the chip enters standby, then the p-channel transistor P1 could turn on when the VCC pin momentarily goes high during an ESD test pulse. That will in turn couple the VCC pin to the high capacitive node B, which may thereby receive charge from the ESD test pulse via that VCC pin. This receiving of charge may occur even though most of the charge is safely shunted to ground by the ESD protection circuitry associated with the VCC pin, and in some cases the amount of charge received by a high capacitive node B can be quite large. After the ESD test, when the power supply voltage has gone back down, the transistor P1 shuts off, isolating the high capacitive node B and its stored charge. N-channel transistor N1 remains off through the entire test operation and thus does not provide a sink to ground for the charge received and stored at node B. The high capacitive node B discharges only very slowly.
Although the amount of stored charge and its associated voltage is not large enough to immediately damage the devices connected to the high capacitive node—that after all is the main reason for having ESD protection circuitry—if a high voltage at node B were to be sustained for a long enough time, it could stress the connected devices such that junction degradation in those devices is possible. Current leakage resulting from junction degradation of any devices can cause circuit malfunction under normal operation.